A compiler that takes a trained YOLO model and produces a chip layout in days — not years.
Every stage above runs on real, open tools — Yosys, OpenROAD, KLayout, Sky130 — not a rendering or a simulation of what a chip might look like.
Most of this industry oversells. Here's exactly what's validated today, pulled straight from the repo's own status checks.
Two ways your trained weights end up on silicon, chosen automatically per layer.
Live activations and line buffers live in a prebuilt Sky130 SRAM macro, banked and tiled to the required word width. Read/write, like memory should be.
Trained weights compile directly into synthesized case logic that Yosys maps onto standard cells — no SRAM, no weight-load path. No weights to load, because the weights are the wires.
Every YOLO model decomposes into a known set of hardware primitives. The Filosic compiler instantiates, sizes, and connects them automatically.
Systolic MAC array with parameterized kernel size, stride, and channel count. Line buffers feed input windows; accumulator tree produces each output pixel. Supported: conv1d, conv2d, grouped conv.
Configurable MaxPool and AveragePool with kernel and stride parameters. Shared datapath selected by a mode flag so only one pool unit is instantiated per model.
ReLU, LeakyReLU, SiLU, Sigmoid — implemented as piecewise-linear approximations or direct lookup. Fused into the convolution pipeline to avoid intermediate memory round-trips.
Nearest-neighbor and bilinear upsampling with configurable scale factor. Bilinear uses a sequential divider and registered beat counters to keep area small.
YOLOv5-style (Conv + FC layers) and YOLOv8-style (split TaskDecouple) heads both supported. The compiler detects the head pattern from the ONNX graph and maps it to the correct hardware template.
Time-multiplexed backend (M4) that runs the whole model through one shared copy of each compute unit. ~174k cells vs ~4M for the spatial design — the path that makes full-model GDS practical.
Sequencer, address generator, and handshake logic that orchestrates data movement between modules. Generated per-model; no microcode, no firmware.
YOLOv5 / v8
v5n, v5nu, v8n, v8s, v8m — compile, close timing, DRC-clean GDSII
YOLOv10n
Validated end-to-end. Hardware boundary at detect-merge output; later ONNX postprocess is software cutoff.
YOLO11n / 12n
Compiled, timed at 20 ns (yolo11n) and 21 ns (yolo12n), GDS emitted
YOLO26n
Validated to detect-merge boundary. ~440k cells, 20 ns timing closed
Custom models
General ONNX graph compiler in design — not limited to YOLO families
Sequential divider in the DFL stage, replacing a combinational variable division that was setting the critical path.
Registered beat counters in the upsample unit, breaking a long comparison chain into pipelined stages.
Running max in DFL instead of a wide combinational reduction tree.
Result: temporal engine closes timing at 20 ns. 5/6 models show positive setup and hold WNS.
| Model | Period | Setup WNS | Hold WNS | Cells | Status |
|---|---|---|---|---|---|
| YOLOv8n | 20 ns | +0.86 ns | +0.35 ns | 162k | PASS |
| YOLOv5nu | 20 ns | +1.03 ns | +0.35 ns | 151k | PASS |
| YOLO11n | 20 ns | +2.41 ns | +0.35 ns | 437k | PASS |
| YOLO12n | 21 ns | +0.33 ns | +0.35 ns | 615k | PASS |
| YOLO26n | 20 ns | +1.77 ns | +0.35 ns | 440k | PASS |
| YOLOv10n | 20 ns* | — | — | 893k | OOM† |
* Closes at 20 ns once timing is repaired, but Yosys produces ~893k cells due to a large-kernel depthwise layer. † Fix is moving input_buf to SRAM macro — tape-out roadmap item.
Dual-PDK support: temporal engine runs on both Sky130 (130 nm, real foundry) and FreePDK45 / Nangate45 (45 nm, ~8× denser, whole model fits at ~28 mm²). See docs →
Compiler-as-a-service. Upload a supported YOLO-family ONNX model, get back synthesizable RTL and a GDSII layout validated bit-exact against your original weights — on the Sky130 open PDK for testing and evaluation.
Talk to us about integration →A standardized chip catalog for lower-volume customers — pre-validated model + package combinations on Sky130 for testing and evaluation.
See what's in the catalog →